Presently the most popular methods of control for DC/DC converters are voltage mode control and current mode control. Such controls may be used with hysteretic converters, and a current mode control for hysteretic converter is described=in U.S. Pat. No. 4,494,074 to Bose, granted Jan. 15, 1985 and entitled “FEEDBACK CONTROL”, the entire contents of which are incorporated herein by reference. Despite this description, hysteretic current mode control remains an obscure technique that few designers use, yet offers advantages in some applications. Hysteretic current mode control (HCMC) offers the tightest and most accurate control of inductor current, and offers excellent transient response to step loads. The advantages of this control technique include: inherent load current limiting; no slope compensation required for duty cycles above 50%; easy loop stability design; and no sub-harmonic oscillation. Additionally, HCMC controls both the average load current and the output voltage.
In spite of these advantages, no straightforward design or analysis of HCMC is available which makes it more difficult to use this mode of control. There are two groups of methods typically utilized to control the switching frequency of HCMC: open loop and closed loop. Open loop methods are easier to implement, however in open loop methods the switching frequency depends upon the power stage circuit topology and components, the input and output voltages and the load. The most precise closed loop frequency control method is to phase lock the converter to a fixed frequency clock. U.S. Pat. No. 5,734,259 to Sisson et al., granted Mar. 31, 1998 and entitled “BALANCED DELTA CURRENT METHOD FOR CURRENT CONTROL IN A HYSTERETIC POWER SUPPLY”, the entire contents of which is incorporated herein by reference, is addressed to a method of using hysteretic current mode control in buck converters. In order to keep the frequency fixed, linear feedback is provided from the input voltage to control the hysteresis window vs. input voltage. However, this method does not provide accurate control since the resultant switching frequency is not ultimately linearly related to the input voltage. In particular the relationship of Sisson's converter is derivable mathematically, as shown in EQ. 1 below, to be:
                    Fsw_buck        =                                            Vout              ·                              (                                  Vin                  -                  Vout                                )                                                    Ih              ·              L              ·              Vin                                =                                    1                              Ih                ·                L                                      ·            Vout            ·                          (                              1                -                                  Vout                  Vin                                            )                                                          EQ        .                                  ⁢        1            where Fsw_buck is the switching frequency of the converter in buck mode, Vout is the output voltage of the converter, Vin is the input voltage of the converter, Ih is the inductor current of the converter and L is the inductance of the inductor of the converter.
In battery application devices it is necessary for the DC/DC converter to operate in a buck mode, buck-boost mode and a boost mode. FIG. 1 illustrates the different stages of such a converter where the x-axis represents time and the y-axis represents voltage. Curve 1 illustrates the battery voltage, denoted VBATT, which is the input voltage of the converter. During time period T1, VBATT is greater than the load voltage, denoted VLOAD and illustrated by line 2, therefore the converter operates in a buck mode. During time period T2, VBATT is close to VLOAD therefore the converter operates in a buck-boost mode. During time period T3, VBATT is less than VLOAD therefore the converter operates in a buck-boost mode.
FIGS. 2A-2C illustrate a high level schematic diagram of a hysteretic current mode control converter according to the prior art. In particular, FIG. 2A illustrates a high level schematic diagram of a hysteretic current mode control converter 10, FIG. 2B illustrates a mode control circuitry 20 arranged to control the mode of converter 10 and FIG. 2C illustrates a phased lock loop (PLL) 30 arranged to adjust the hysteresis levels of converter 10, the figures being described together. Converter 10 comprises: mode control circuitry 20; PLL 30; an input capacitor CIN; a first NMOSFET M1; a second NMOSFET M2; a third NMOSFET M3; a fourth NMOSFET M4; an inductor L1; a sense resistor RS; an output capacitor COUT; an output voltage error circuitry 40; a low threshold voltage source 50; a high threshold voltage source 60; a control circuitry 70; a current sense amplifier CSA; and an external clock 80. Mode control circuitry 20 comprises: a buck mode comparator 90; a buck mode voltage source 100; a boost mode comparator 110; a boost mode voltage source 120; and a buck-boost NOR gate 130. PLL 30 comprises: a first PLL D flip flop D1; a second PLL D flip flop D2; a PLL NAND gate 140; a first PLL electronically controlled switch 150; a second PLL electronically controlled switch 160; a first PLL current source 170; a second PLL current source 180; and a PLL capacitor CP. Output voltage error circuitry 40 comprises: a voltage divider 190; a transconductance amplifier TCA; a TCA reference voltage source 200; an error circuitry resistor RE; and an error circuitry capacitor CE. Control circuitry 70 comprises: a switching control unit 210; a high threshold comparator 220; a low threshold comparator 230; and a control SR flip flop SR1.
A first end of input capacitor CIN is coupled to the input of converter 10 and to the drain of first NMOSFET M1 and a second end of input capacitor CIN is coupled to a common potential. The voltage at the input of converter 10 is denoted Vin. The source of first NMOSFET M1 is coupled to a first end of inductor L1 and to the drain of second NMOSFET M2 and the source of second NMOSFET M2 is coupled to the common potential. A second end of inductor L1 is coupled to a first end of sense resistor RS and a second end of sense resistor RS is coupled to the drain of third NMOSFET and to the drain of fourth NMOSFET M4. The source of third NMOSFET M3 is coupled to the common potential and the source of fourth NMOSFET M4 is coupled to a first end of output capacitor COUT, to a first end of voltage divider 190 and to the output of converter 10, the voltage at the output of converter 10 denoted Vout.
A divided voltage node of voltage divider 190 is coupled to a first input of transconductance amplifier TCA and a second end of voltage divider 190 is coupled to the common potential. A second input of transconductance amplifier TCA is coupled to a first end of TCA reference voltage source 200 and a second end of TCA reference voltage source 200 is coupled to the common potential. The output of transconductance amplifier TCA is coupled to a first end of error circuitry resistor RE, to the positive end of low threshold voltage source 50 and to the negative end of high threshold voltage source 60. The negative end of low threshold voltage source 50 is coupled to the non-inverting input of low threshold comparator 230 and the positive end of high threshold voltage source 60 is coupled to the inverting input of high threshold comparator 220. The inverting input of low threshold comparator 230 and the non-inverting input of high threshold comparator 220 are each coupled to the output of current sense amplifier CSA. The non-inverting input of current sense amplifier CSA is coupled to the first end of sense resistor RS and the inverting input of current sense amplifier CSA is coupled to the second end sense resistor RS. The output of high threshold comparator 220 is coupled to the reset input of control SR flip flop SR1 and the output of low threshold comparator 230 is coupled to the set input of control SR flip flop SR1. The Q bar output of control SR flip flop SR1 is coupled to a respective input of switching control unit 210 and the Q output of control SR flip flop SR1 is coupled to a respective input of switching control unit 210 and to the clock input of first PLL D flip flop D1 and is denoted SR1Q.
The output of external clock 80 is coupled to the clock input of second PLL D flip flop D2 and the D input of each of first PLL D flip flop D1 and second PLL D flip flop D2 is coupled to a supply voltage, denoted VCC. The Q output of first PLL D flip flop D1 is coupled to a first input of PLL NAND gate 140 and to a control input of first PLL electronically controlled switch 150. The Q output of second PLL D flip flop D2 is coupled to a second input of PLL NAND gate 140 and to a control input of second PLL electronically controlled switch 160. The output of PLL NAND gate 140 is coupled to the clear input each of first PLL D flip flop D1 and second PLL D flip flop D2. The output of first PLL current source 170 is coupled to a first terminal of first PLL electronically controlled switch 150 and the input of first PLL current source 170 is coupled to supply voltage VCC. A second terminal of first PLL electronically controlled switch 150 is coupled to a first end of PLL capacitor CP and to a first terminal of second PLL electronically controlled switch 160. A second terminal of second PLL electronically controlled switch 160 is coupled to the input of second PLL current source 180 and the output of second PLL current source 180 is coupled to the common potential. A second end of PLL capacitor CP is coupled to the common potential. The first end of PLL capacitor CP, defining the output of PLL 30 and denoted ΔH, is coupled to a control input of low threshold voltage source 50 and high threshold voltage source 60.
A first input of mode control circuitry 20 is coupled to input voltage Vin and a second input of mode control circuitry 20 is coupled to output voltage Vout. In particular, the non-inverting input of buck mode comparator 90 and the inverting input of boost mode comparator 110 are each coupled to input voltage Vin; and the negative end of buck mode voltage source 100 and the positive end of boost mode voltage source 120 are each coupled to output voltage Vout. The positive end of buck mode voltage source 100 is coupled to the inverting input of buck mode comparator 90 and the output of buck mode comparator 90 is coupled to a first input of buck-boost NOR gate 130 and to a respective input of switching control unit 210, and is denoted BUCK. The negative end of boost mode voltage source 120 is coupled to the non-inverting input of boost mode comparator 110 and the output of boost mode comparator 110 is coupled to a second input of buck-boost NOR gate 130 and to a respective input of switching control unit 210, and is denoted BOOST. The output of buck-boost NOR gate 130 is coupled to a respective input of switching control unit 210, and is denoted BUCK-BOOST.
In operation, when input voltage Vin is greater than output voltage Vout by at least the offset generated by buck mode voltage source 100 the output of buck mode comparator 90 is high and switching control unit 210 is arranged to operate in a buck mode. In the buck mode, switching control unit 210 is arranged to alternately couple inductor L1 between the input of converter 10 and the output of converter 10 and couple inductor L1 between the output of converter 10 and the common potential, responsive to the current flowing through inductor L1, denoted Ih, and the output of output voltage error circuitry 40. In particular, a portion of output voltage Vout is compared to the voltage output by TCA reference voltage source 200, denoted VREF. The difference between the portion of output voltage Vout and reference voltage VREF is output by TCA reference voltage source 200 as a current which charges and discharges error circuitry capacitor CE, the voltage across error circuitry resistor RE and error circuitry capacitor CE denoted error voltage EA. Particularly, in the event that output voltage Vout is less than reference voltage VREF, the current output by TCA reference voltage source 200 charges error circuitry capacitor CE and in the event that output voltage Vout is greater than reference voltage VREF, the current output by TCA reference voltage source 200 discharges error circuitry capacitor CE.
A voltage representation of the current flowing through inductor L1, denoted VC, is output by current sense amplifier CSA and compared to error voltage EA offset by each of low threshold voltage source 50 and high threshold voltage source 60. In the event that voltage representation VC is less than error voltage EA offset by low threshold voltage source 50, control SR flip flop SR1 is set and switching control unit 210 is arranged to: close first NMOSFET M1 and fourth NMOSFET M4; and open second NMOSFET M2 and third NMOSFET M3. The voltage across inductor L1 is thus Vin−Vout and the current thereacross, denoted Ih, increases at a rate of (Vin−Vout)/L. In the event that voltage representation VC is greater than error voltage EA offset by high threshold voltage source 60, control SR flip flop SR1 is reset and switching control unit 210 is arranged to: open first NMOSFET M1 and third NMOSFET M3; and close second NMOSFET M2 and fourth NMOSFET M4. The voltage across inductor L1 is thus −Vout and current Ih decreases at a rate of Vout/L. Control circuitry 70 thus provides hysteretic control of converter 10 since voltage representation VC is compared to a positive and negative offset of error voltage EA and the position of the switches are adjusted responsive to the offsets of error voltage EA.
In the event that input voltage Vin is not greater than output voltage Vout by the offset of buck mode voltage source 100 and is not less than output voltage Vout by the offset of boost mode voltage source 120, the output of buck-boost mode NOR gate 130 is high and control circuitry 70 is arranged to operate in a buck-boost mode. In the buck-boost mode, switching control unit 210 is arranged to alternately couple inductor L1 between the input of converter 10 and the common potential and couple inductor L1 between the output of converter 10 and the common potential. In particular, in the event that voltage representation VC is less than error voltage EA offset by low threshold voltage source 50, control SR flip flop SR1 is set and switching control unit 210 is arranged to: close first NMOSFET M1 and third NMOSFET M3; and open second NMOSFET M2 and fourth NMOSFET M4. The voltage across inductor L1 is thus Vin and current Ih increases at a rate of Vin/L. In the event that voltage representation VC is greater than error voltage EA offset by high threshold voltage source 60, control SR flip flop SR1 is reset and switching control unit 210 is arranged to: open first NMOSFET M1 and third NMOSFET M3; and close second NMOSFET M2 and fourth NMOSFET M4. The voltage across inductor L1 is thus −Vout and current Ih decreases at a rate of Vout/L.
In the event that input voltage Vin is less than output voltage Vout by at least the offset of boost mode voltage source 120, the output of boost mode comparator 110 is high and control circuitry 70 is arranged to operate in a boost mode. In the boost mode, switching control unit 210 is arranged to alternately couple inductor L1 between the input of converter 10 and the common potential and couple inductor L1 between the input of converter 10 and the output of converter 10. In particular, in the event that voltage representation VC is less than error voltage EA offset by low threshold voltage source 50, control SR flip flop SR1 is set and switching control unit 210 is arranged to: close first NMOSFET M1 and third NMOSFET M3; and open second NMOSFET M2 and fourth NMOSFET M4. The voltage across inductor L1 is thus Vin and current Ih increases at a rate of Vin/L. In the event that voltage representation VC is greater than error voltage EA offset by high threshold voltage source 60, control SR flip flop SR1 is reset and switching control unit 210 is arranged to: open second NMOSFET M2 and third NMOSFET M3; and close first NMOSFET M1 and fourth NMOSFET M4. The voltage across inductor L1 is thus Vin−Vout and current Ih decreases at a rate (Vout−Vin)/L.
Since the switching frequency of converter 10 is responsive to output voltage Vout and inductor Ih, the switching frequency is not fixed. A non-fixed switching frequency causes random noise and is therefore not desired. PLL 30 is arranged to cause converter 10 to maintain a fixed frequency. In particular, each time control SR flip flop SR1 is set, the Q output of first PLL flip flop D1 is arranged to output a logical high signal and first PLL electronically controlled switch 150 is closed responsive to the logical high signal. First PLL current source 170 is arranged to output a current thereby charging PLL capacitor CP. At the rising edge of external clock 80, denoted CLK, the Q output of second PLL flip flop D2 is arranged to output a logical high signal and second PLL electronically controlled switch 160 is closed responsive to the received logical high signal. Second PLL current source 180 is arranged to output a current thereby discharging PLL capacitor CP. When the outputs of both first PLL flip flop D1 and second PLL flip flop D2 both output logical high signals, PLL NAND gate 140 is arranged to clear first PLL flip flop D1 and second PLL flip flop D2.
Output ΔH of PLL 30 is arranged to adjust the value of the voltage output by low threshold voltage source 50 and high threshold voltage source 60. An increase in ΔH causes an increase in the voltage output by low threshold voltage source 50 and high threshold voltage source 60, thereby increasing the high and low offsets of error voltage EA, and a decrease in ΔH causes a decrease in the voltage output by low threshold voltage source 50 and high threshold voltage source 60, thereby decreasing the offsets of error voltage EA. An increase in the offsets of error voltage EA causes the switching frequency of converter 10 to decrease and a decrease in the offsets of error voltage EA causes the switching frequency of converter 10 to increase. The adjustment of the offsets of error voltage EA drives the switching frequency of converter 10 to be equal to the fixed frequency of external clock 80 over time.
FIG. 2D illustrates a graph of inductor current Ih of converter 10 as a function of input voltage Vin of converter 10, where the x-axis represents voltage and the y-axis represents current. As described above, over time input voltage Vin may decrease responsive to battery discharge and converter 10 operates in a first period, denoted P1, in the buck mode as long as Vin is appreciably greater than Vout. As input voltage Vin continues to decrease, and Vin approaches Vout, converter 10 operates in a second period, denoted P2, in the buck-boost mode. As input voltage Vin continues to decrease, to be appreciably less than Vout, converter 10 operates in a third period, denoted P3, in the boost mode. As illustrated by curve 250, when converter 10 switches between the buck mode of period P1 and the buck-boost mode of period P2; and when converter 10 switches between the buck-boost mode of period P2 and the boost mode of period P3, there is a discontinuity in inductor current Ih. In particular, during the buck mode inductor current Ih is given as:
                    Ih        =                              1                          Fsw              ·              L                                ·                      [                          Vout              ·                              (                                  1                  -                                      Vout                    Vin                                                  )                                      ]                                              EQ        .                                  ⁢        2            during the buck-boost mode inductor current Ih is given as:
                    Ih        =                              1                          Fsw_buck              ⁢              _boost                                ·                                    Vin              ·              Vout                                      L              ·                              (                                  Vin                  +                  Vout                                )                                                                        EQ        .                                  ⁢        3            and in the boost mode inductor current Ih is given as:
                    Ih        =                              1                          Fsw              ·              L                                ·                      [                          Vin              ·                              (                                  1                  -                                      Vin                    Vout                                                  )                                      ]                                              EQ        .                                  ⁢        4            where Fsw is the switching frequency of converter 10 which is fixed, as described above, responsive to the PLL.
FIG. 2E is a simplified illustration of inductor current Ih, where the x-axis denotes time and the y-axis denotes current. As shown, during period P1, when converter 10 is in the buck mode, inductor Ih increases at a rate of (Vin−Vout)/L when inductor L1 is coupled between input voltage Vin and output voltage Vout and decreases at a rate of Vout/L when inductor L1 is coupled between output voltage Vout and the common potential. During period P2, when converter 10 is in the buck-boost mode, inductor Ih increases at a rate of Vin/L when inductor L1 is coupled between input voltage Vin and the common potential and decreases at a rate of Vout/L when inductor L1 is coupled between output voltage Vout and the common potential. During period P3, when converter 10 is in the boost mode, inductor Ih increases at a rate of Vin/L when inductor L1 is coupled between input voltage Vin and the common potential and decreases at a rate of (Vout−Vin)/L when inductor L1 is coupled between input voltage Vin and output voltage Vout. As shown by lines 251 and 252, during the buck mode of converter 10 PLL 30 decreases the hysteretic offsets of error voltage VA. As converter 10 switches to the buck-boost mode the peak of inductor current Ih and therefore the output ripple amplitude suddenly increases because of the increase in the inductor voltage. As converter 10 switches to the boost mode the peak of inductor current Ih and therefore the output ripple amplitude suddenly decreases because of the reduction in the inductor voltage. Disadvantageously, the discontinuation in inductor current Ih causes unwanted noise.
There is thus a long felt need for a hysteretic current mode control converter which provides for an inductor current with a reduced discontinuation when the converter switches between modes.